FIG. 1 shows a diagram of a conventional static pullup circuit 100 commonly used in CMOS integrated circuits for high speed applications. The term CMOS is also used herein to refer to complementary MOS structures using silicon gate technologies. An N-tree 110 operates to pull down the voltage at an output line 101 when active and stops pulling down the voltage at output line 101 when not active. Output line 101 is coupled to pullup circuit 100 at an internal node 120. Internal node 120 is connected to CMOS inverter 130 by an input lead 131. Thus, the logic level on internal node 120 is inverted by inverter 130 at an output lead 132. Output lead 132 is connected to the gate of pulldown P-channel field effect transistor (FET) 140 via feed back line 141. P-channel FET 140 has a source connected to internal node 120 and a drain held at ground potential. Thus, the output signal generated by inverter 130 feeds back to the gate of P-channel FET 140, thereby turning P-channel FET 140 on or off.
A P-channel FET 150, having a source connected to a Vdd voltage source and a drain connected to internal node 120 serves as a pullup device. P-channel FET 150 receives a signal PWR.sub.-- BYPASS on a gate 151. In normal operation, signal PWR.sub.-- BYPASS is kept at a logic low level (i.e., deasserted) by mode control circuitry (not shown), thereby causing P-channel FET to turn on. Consequently, a voltage divider is formed by pullup P-channel FET 150 and pulldown P-channel FET 140 through internal node 120, which determines the voltage at which node 120 is held when N-tree 110 is not active.
The PWR.sub.-- BYPASS signal is used to place pullup circuit 100 in a power bypass mode, which stops all power consumption by pullup circuit 100. Thus, when pullup circuit 100 is not in operation (e.g., during testing) the PWR.sub.-- BYPASS signal can be asserted (i.e., driven to a logic high level) to enter the power bypass mode. When the PWR.sub.-- BYPASS signal is asserted, pullup P-channel FET 150 is turned off, thereby cutting off any DC current path through node 120 from the voltage Vdd source and the source of ground potential. As a result, substantially no power is consumed by pullup circuit 100. Further, an N-channel FET 160, having a drain connected to node 120 and a source held at ground potential, receives the PWR.sub.-- BYPASS signal at a gate 161. Thus, when the PWR.sub.-- BYPASS signal is asserted, pull-down N-channel FET 160 is activated, thereby pulling down the voltage at internal node 120 to a logic low level. The logic low voltage level at internal node 120 causes inverter 130 to output a logic high output signal on output lead 132, thereby providing a deterministic high output state for pullup circuit 100 when in the power bypass mode.
Pullup circuit 100 operates as follows. When inverter 130 is generating a logic high signal on output lead 132 (i.e, N-tree 110 is pulling down the voltage at internal node 120), the gate of pulldown P-channel FET 140 receives the logic high signal via line 141 and is turned off. The "low" voltage at node 120 is determined by the device ratio of pullup FET 150 to N-tree 110, which is designed to be below the threshold voltage of inverter 130 (i.e., the voltage above which inverter 130 generates a logic low output signal and below which inverter 130 generates a logic high output signal).
Then, when N-tree 110 is not active (i.e., N-tree 110 no longer pulls down the voltage at internal node 120), pullup FET 150, begins to pull up the voltage at internal node 120. Once the voltage of internal node 120 rises above the threshold voltage of inverter 130, inverter 130 generates a logic low signal, which causes pulldown FET 140 to become relatively more conductive (i.e., able to conduct more current). As a result, pulldown FET 140 begins to reduce the pull up effect of pullup FET 150, causing the voltage at node 120 to only rise slightly above the threshold voltage of inverter 130. Thus, when N-tree 110 later receives an input signal or signals (not shown) causing N-tree 110 to pull down the voltage at internal node 120, N-tree 110 does not have as much voltage to pull down, thereby reducing the pulldown time.
Consequently, the ratio of the sizes of P-channel FETs 140 and 150 directly determines the "high" voltage level of internal node 120. The designer can attempt to optimize the pulldown and pullup speeds by adjusting the size ratio of P-channel FETs 140 and 150, basically "trading off" pullup speed for pulldown speed.